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3.3v 4k/8k/16k x 16/18 dual-port static ram cy7c024av/025av/026av cy7c0241av/0251av/036av preliminary cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 november 29, 1999 1 features ? true dual-ported memory cells which allow simulta- neous access of the same memory location 4/8/16k x 16 organization (cy7c024av/025av/026av) 4/8k x 18 organization (cy7c0241av/0251av) 16k x 18 organization (cy7c036av) 0.35-micron cmos for optimum speed/power high-speed access: 15 [1] /20/25 ns low operating power ? active: i cc = 115 ma (typical) ? standby: i sb3 = 10 a (typical) fully asynchronous operation automatic power-down expandable data bus to 32/36 bits or more using master/ slave chip select when using more than one device on-chip arbitration logic semaphores included to permit software handshaking between ports int flag for port-to-port communication separate upper-byte and lower-byte control pin select for master or slave commercial and industrial temperature ranges available in 100-pin tqfp pin-compatible and functionally equivalent to idt70v24, 70v25, and 7v0261. notes: 1. call for availability. 2. i/o 8 ?i/o 15 for x16 devices; i/o 9 ?i/o 17 for x18 devices. 3. i/o 0 ?i/o 7 for x16 devices; i/o 0 ?i/o 8 for x18 devices. 4. a 0 ?a 11 for 4k devices; a 0 ?a 12 for 8k devices; a 0 ?a 13 for 16k devices. 5. busy is an output in master mode and an input in slave mode. r/w l oe l i/o 8/9l ?i/o 15/17l i/o control address decode a 0l ?a 11/12/13l ce l oe l r/w l busy l i/o control ce l interrupt semaphore arbitration sem l int l m/s ub l lb l i/o 0l ?i/o 7/8l r/w r oe r i/o 8/9l ?i/o 15/17r ce r ub r lb r i/o 0l ?i/o 7/8r ub l lb l logic block diagram a 0l ?a 11/1213l true dual-ported ram array a 0r ?a 11/12/13r ce r oe r r/w r busy r sem r int r ub r lb r address decode a 0r ?a 11/12/13r [2] [2] [3] [3] [5] [5] 12/13/14 8/9 8/9 12/13/14 8/9 8/9 12/13/14 12/13/14 [4] [4] [4] [4] for the most recent information, visit the cypress web site at www.cypress.com
cy7c024av/025av/026av cy7c0241av/0251av/036av 2 preliminary functional description the cy7c024av/025av/026av and cy7c0241av/0251av / 036av are low-power cmos 4k, 8k, and 16k x16/18 dual- port static rams. various arbitration schemes are included on the devices to handle situations when multiple processors ac- cess the same piece of data. two ports are provided, permit- ting independent, asynchronous access for reads and writes to any location in memory. the devices can be utilized as stan- dalone 16/18-bit dual-port static rams or multiple devices can be combined in order to function as a 32/36-bit or wider mas- ter/slave dual-port static ram. an m/s pin is provided for im- plementing 32/36-bit or wider memory applications without the need for separate master and slave devices or additional dis- crete logic. application areas include interprocessor/multipro- cessor designs, communications status buffering, and dual- port video/graphics memory. each port has independent control pins: chip enable (ce ), read or write enable (r/w ), and output enable (oe ). two flags are provided on each port (busy and int ). busy sig- nals that the port is trying to access the same location currently being accessed by the other port. the interrupt flag (int ) per- mits communication between ports or systems by means of a mail box. the semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. the semaphore logic is comprised of eight shared latches. only one side can control the latch (semaphore) at any time. control of a semaphore indicates that a shared re- source is in use. an automatic power-down feature is con- trolled independently on each port by a chip select (ce ) pin. the cy7c024av/025av/026av and cy7c0241av/0251av/ 036av are available in 100-pin thin quad plastic flatpacks (tqfp). pin configurations notes: 6. a 12l on the cy7c025av. 7. a 12r on the cy7c025av. top view 100-pin tqfp 100 99 97 98 96 2 3 1 42 41 59 60 61 12 13 15 14 16 4 5 40 39 95 94 17 26 9 10 8 7 6 11 27 28 30 29 31 32 35 34 36 37 38 33 67 66 64 65 63 62 68 69 70 75 73 74 72 71 89 88 86 87 85 93 92 84 nc nc nc nc a 5l a 4l int l a 2l a 0l busy l gnd int r a 0r a 1l nc nc nc nc i/o 10l i/o 11l i/o 15l v cc gnd i/o 1r i/o 2r v cc 90 91 a 3l m/s busy r i/o 14l gnd i/o 12l i/o 13l a 1r a 2r a 3r a 4r nc nc nc nc i/o 3r i/o 4r i/o 5r i/o 6r nc nc nc nc 18 19 20 21 22 23 24 25 83 82 81 80 79 78 77 76 58 57 56 55 54 53 52 51 43 44 45 46 47 48 49 50 i/o 9l i/o 8l i/o 7l i/o 6l i/o 5l i/o 4l i/o 3l i/o 2l gnd i/o 1l i/o 0l oe l sem l v cc ce l ub l lb l nc a 11l a 10l a 9l a 8l a 7l a 6l i/o 0r i/o 7r i/o 8r i/o 9r i/o 10r i/o 11r i/o 12r i/o 13r i/o 14r gnd i/o 15r ? r r/w r gnd sem r ce r ub r lb r nc a 11r a 10r a 9r a 8r a 7r a 6r a 5r cy7c024av (4k x 16) r/w l [6] [7] cy7c025av (8k x 16)
cy7c024av/025av/026av cy7c0241av/0251av/036av 3 preliminary pin configurations (continued) notes: 8. a 12l on the cy7c0251av. 9. a 12r on the cy7c0251avc. top view 100-pin tqfp 100 99 97 98 96 2 3 1 42 41 59 60 61 12 13 15 14 16 4 5 40 39 95 94 17 26 9 10 8 7 6 11 27 28 30 29 31 32 35 34 36 37 38 33 67 66 64 65 63 62 68 69 70 75 73 74 72 71 89 88 86 87 85 93 92 84 nc nc nc nc a 5l a 4l int l a 2l a 0l busy l gnd int r a 0r a 1l nc nc i/o 11l i/o 12l i/o 16l v cc gnd i/o 1r i/o 2r v cc 90 91 a 3l m/s busy r i/o 15l gnd i/o 13l i/o 14l a 1r a 2r a 3r a 4r nc nc nc nc i/o 3r i/o 4r i/o 5r i/o 6r nc nc 18 19 20 21 22 23 24 25 83 82 81 80 79 78 77 76 58 57 56 55 54 53 52 51 43 44 45 46 47 48 49 50 i/o 9l i/o 7l i/o 6l i/o 5l i/o 4l i/o 3l i/o 2l i/o 10l gnd i/o 1l i/o 0l oe l sem l v cc ce l ub l lb l nc a 11l a 10l a 9l a 8l a 7l a 6l i/o 0r i/o 7r i/o 16r i/o 9r i/o 10r i/o 11r i/o 12r i/o 13r i/o 14r gnd i/o 15r oe r r/w r gnd sem r ce r ub r lb r nc a 11r a 10r a 9r a 8r a 7r a 6r a 5r cy7c0241av (4k x 18) i/o 8l i/o 17l i/o 8r i/o 17r r/w l [9] [8] 1 3 2 92 91 90 84 85 87 86 88 89 83 82 81 76 78 77 79 80 93 94 95 96 97 98 99 100 59 60 61 67 66 64 65 63 62 68 69 70 75 73 74 72 71 nc nc nc a6l a5l a4l int l a2l a0l gnd m/s a0r a1r a1l a3l busy r int r a2r a3r a4r a5r nc nc nc busy l 58 57 56 55 54 53 52 51 cy7c026av (16k x 16) nc nc nc nc i/o10l i/o11l i/o15l i/o13l i/o14l gnd i/o0r vcc i/o3r gnd i/o12l i/o1r i/o2r i/o4r i/o5r i/o6r nc nc nc nc vcc 17 16 15 9 10 12 11 13 14 8 7 6 4 5 18 19 20 21 22 23 24 25 i/o9l i/o8l i/o7l i/o6l i/o5l i/o4l i/o0l i/o2l i/o1l vcc r/w l ub l lb l gnd i/o3l sem l ce l a113l a12l a11l a10l a9l a8l a7l oe l 34 35 36 42 41 39 40 38 37 43 44 45 50 48 49 47 46 a6r a7r a8r a9r a10r a11r ce r a13r ub r gnd r/w r gnd i/o14r lb r a12r oe r i/o15r i/o13r i/o12r i/o11r i/o10r i/o9r i/o8r i/o7r sem r 33 32 31 30 29 28 27 26 cy7c0251av (8k x 18)
cy7c024av/025av/026av cy7c0241av/0251av/036av 4 preliminary pin configurations (continued) selection guide cy7c024av/025av/ 026av cy7c0241av/0251av/ 036av -15 [1] cy7c024av/025av/ 026av cy7c0241av/0251av/ 036av -20 cy7c024av/025av/ 026av cy7c0241av/0251av/ 036av -25 maximum access time (ns) 15 20 25 typical operating current (ma) 125 120 115 typical standby current for i sb1 (ma) (both ports ttl level) 35 35 30 typical standby current for i sb3 ( a) (both ports cmos level) 10 a 10 a 10 a shaded areas contain advance information. top view 100-pin tqfp 100 99 97 98 96 2 3 1 42 41 59 60 61 12 13 15 14 16 4 5 40 39 95 94 17 26 9 10 8 7 6 11 27 28 30 29 31 32 35 34 36 37 38 33 67 66 64 65 63 62 68 69 70 75 73 74 72 71 89 88 86 87 85 93 92 84 nc nc nc a 5l a 4l int l a 2l a 0l busy l gnd int r a 0r a 1l nc nc i/o 11l i/o 12l i/o 16l v cc gnd i/o 1r i/o 2r v cc 90 91 a 3l m/s busy r i/o 15l gnd i/o 13l i/o 14l a 1r a 2r a 3r a 4r nc nc nc i/o 3r i/o 4r i/o 5r i/o 6r nc nc 18 19 20 21 22 23 24 25 83 82 81 80 79 78 77 76 58 57 56 55 54 53 52 51 43 44 45 46 47 48 49 50 i/o 9l i/o 7l i/o 6l i/o 5l i/o 4l i/o 3l i/o 2l i/o 10l gnd i/o 1l i/o 0l oe l sem l v cc ce l ub l lb l a 11l a 10l a 9l a 8l a 7l a 6l i/o 0r i/o 7r i/o 16r i/o 9r i/o 10r i/o 11r i/o 12r i/o 13r i/o 14r gnd i/o 15r oe r r/w r gnd sem r ce r ub r lb r a 11r a 10r a 9r a 8r a 7r a 6r a 5r i/o 8l i/o 17l i/o 8r i/o 17r r/w l cy7c036av (16k x 18) a 13l a 13r a 12l a 12r
cy7c024av/025av/026av cy7c0241av/0251av/036av 5 preliminary maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ? 65 c to +150 c ambient temperature with power applied ............................................. ? 55 c to +125 c supply voltage to ground potential ............... ? 0.5v to +4.6v dc voltage applied to outputs in high z state ........................... ? 0.5v to v cc +0.5v dc input voltage [10] ................................. ? 0.5v to v cc +0.5v output current into outputs (low) ............................. 20 ma static discharge voltage .......................................... >2001v latch-up current.................................................... >200 ma notes: 10. pulse width < 20 ns. 11. industrial parts are available in cy7c026av and cy7c036av only. pin definitions left port right port description ce l ce r chip enable r/w l r/w r read/write enable oe l oe r output enable a 0l ? a 13l a 0r ? a 13r address (a 0 ? a 11 for 4k devices; a 0 ? a 12 for 8k devices; a 0 ? a 13 for 16k) i/o 0l ? i/o 17l i/o 0r ? i/o 17r data bus input/output sem l sem r semaphore enable ub l ub r upper byte select (i/o 8 ? i/o 15 for x16 devices; i/o 9 ? i/o 17 for x18 devices) lb l lb r lower byte select (i/o 0 ? i/o 7 for x16 devices; i/o 0 ? i/o 8 for x18 devices) int l int r interrupt flag busy l busy r busy flag m/s master or slave select v cc power gnd ground nc no connect operating range range ambient temperature v cc commercial 0 c to +70 c 3.3v 300 mv industrial [11] ? 40 c to +85 c 3.3v 300 mv shaded areas contain advance information.
cy7c024av/025av/026av cy7c0241av/0251av/036av 6 preliminary notes: 12. f max = 1/t rc = all inputs cycling at f = 1/t rc (except output enable). f = 0 means no address or control lines change. this applies only to inputs at cmos level standby i sb3 . 13. tested initially and after any design or process changes that may affect these parameters. electrical characteristics over the operating range parameter description cy7c024av/025av/026av cy7c0241av/0251av/036av unit -15 [1] -20 -25 min. typ. max. min. typ. max. min. typ. max. v oh output high voltage (v cc =3.3v) 2.4 2.4 2.4 v v ol output low voltage 0.4 0.4 0.4 v v ih input high voltage 2.0 2.0 2.0 v v il input low voltage 0.8 0.8 0.8 v i oz output leakage current ? 10 10 ? 10 10 ? 10 10 a i ix input leakage current ? 10 10 ? 10 10 ? 10 10 a i cc operating current (v cc = max., i out = 0 ma) outputs disabled com ? l. 125 185 120 175 115 165 ma ind. [11] 135 185 ma i sb1 standby current (both ports ttl level) ce l & ce r v ih , f = f max com ? l. 35 50 35 45 30 40 ma ind. [11] 40 50 ma i sb2 standby current (one port ttl level) ce l | ce r v ih , f = f max com ? l. 80 120 75 110 65 95 ma ind. [11] 75 105 ma i sb3 standby current (both ports cmos level) ce l & ce r v cc ? 0.2v, f = 0 com ? l. 10 500 10 500 10 500 a ind. [11] 10 500 a i sb4 standby current (one port cmos level) ce l | ce r v ih , f = f max [12] com ? l. 75 105 70 95 60 80 ma ind. [11] 70 90 ma shaded areas contain advance information. capacitance [13] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 3.3v 10 pf c out output capacitance 10 pf ac test loads and waveforms 3.0v gnd 90% 90% 10% 3ns 3 ns 10% all input pulses (a) normal load (load 1) r1 = 590 ? 3.3v output r2 = 435 ? c= 30 pf v th =1.4v output c= 30pf (b) th venin equivalent (load 1) (c) three-state delay (load 2) r1 = 590 ? r2 = 435 ? 3.3v output c= 5pf r th =250 ? including scope and jig) (used for t lz , t hz , t hzwe , & t lzwe
cy7c024av/025av/026av cy7c0241av/0251av/036av 7 preliminary switching characteristics over the operating range [14] parameter description cy7c024av/025av/026av cy7c0241av/0251av/036av unit -15 [1] -20 -25 min. max. min. max. min. max. read cycle t rc read cycle time 15 20 25 ns t aa address to data valid 15 20 25 ns t oha output hold from address change 3 3 3 ns t ace [15] ce low to data valid 15 20 25 ns t doe oe low to data valid 10 12 13 ns t lzoe [16, 17, 18] oe low to low z 3 3 3 ns t hzoe [16, 17, 18] oe high to high z 10 12 15 ns t lzce [16, 17, 18] ce low to low z 3 3 3 ns t hzce [16, 17, 18] ce high to high z 10 12 15 ns t pu [18] ce low to power-up 0 0 0 ns t pd [18] ce high to power-down 15 20 25 ns t abe [15] byte enable access time 15 20 25 ns write cycle t wc write cycle time 15 20 25 ns t sce [15] ce low to write end 12 15 20 ns t aw address valid to write end 12 15 20 ns t ha address hold from write end 0 0 0 ns t sa [15] address set-up to write start 0 0 0 ns t pwe write pulse width 12 15 20 ns t sd data set-up to write end 10 15 15 ns t hd data hold from write end 0 0 0 ns t hzwe [17, 18] r/w low to high z 10 12 15 ns t lzwe [17, 18] r/w high to low z 3 3 0 ns t wdd [19] write pulse to data delay 30 45 50 ns t ddd [19] write data valid to read data valid 25 30 35 ns notes: 14. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3 .0v, and output loading of the specified i oi /i oh and 30-pf load capacitance. 15. to access ram, ce =l, ub =l, sem =h. to access semaphore, ce =h and sem =l. either condition must be valid for the entire t sce time. 16. at any given temperature and voltage condition for any given device, t hzce is less than t lzce and t hzoe is less than t lzoe . 17. test conditions used are load 3. 18. this parameter is guaranteed but not tested. for information on port-to-port delay through ram cells from writing port to re ading port, refer to read timing with busy waveform. 19. for information on port-to-port delay through ram cells from writing port to reading port, refer to read timing with busy wa veform.
cy7c024av/025av/026av cy7c0241av/0251av/036av 8 preliminary data retention mode the cy7c024av/025av/026av and cy7c0241av/0251av/ 036av are designed with battery backup in mind. data reten- tion voltage and supply current are guaranteed over tempera- ture. the following rules ensure data retention: 1. chip enable (ce ) must be held high during data retention, with- in v cc to v cc ? 0.2v. 2. ce must be kept between v cc ? 0.2v and 70% of v cc during the power-up and power-down transitions. 3. the ram can begin operation >t rc after v cc reaches the minimum operating voltage (3.0 volts). notes: 20. test conditions used are load 2. 21. t bdd is a calculated parameter and is the greater of t wdd ? t pwe (actual) or t ddd ? t sd (actual). 22. ce = v cc , v in = gnd to v cc , t a = 25 c. this parameter is guaranteed but not tested. busy timing [20] t bla busy low from address match 15 20 20 ns t bha busy high from address mismatch 15 20 20 ns t blc busy low from ce low 15 20 20 ns t bhc busy high from ce high 15 17 17 ns t ps port set-up for priority 5 5 5 ns t wb r/w high after busy (slave) 0 0 0 ns t wh r/w high after busy high (slave) 13 15 17 ns t bdd [21] busy high to data valid 15 20 25 ns interrupt timing [20] t ins int set time 15 20 20 ns t inr int reset time 15 20 20 ns semaphore timing t sop sem flag update pulse (oe or sem ) 10 10 12 ns t swrd sem flag write to read time 5 5 5 ns t sps sem flag contention window 5 5 5 ns t saa sem address access time 15 20 25 ns switching characteristics over the operating range [14] (continued) parameter description cy7c024av/025av/026av cy7c0241av/0251av/036av unit -15 [1] -20 -25 min. max. min. max. min. max. timing parameter test conditions [22] max. unit icc dr1 @ vcc dr = 2v 50 a data retention mode 3.0v 3.0v v cc > 2.0v v cc to v cc ? 0.2v v cc ce t rc v ih
cy7c024av/025av/026av cy7c0241av/0251av/036av 9 preliminary switching waveforms notes: 23. r/w is high for read cycles. 24. device is continuously selected ce = v il and ub or lb = v il . this waveform cannot be used for semaphore reads. 25. oe = v il . 26. address valid prior to or coincident with ce transition low. 27. to access ram, ce = v il , ub or lb = v il , sem = v ih . to access semaphore, ce = v ih , sem = v il . t rc t aa t oha data valid previous data valid data out address t oha read cycle no.1 (either port address access) [23, 24, 25] t ace t lzoe t doe t hzoe t hzce data valid t lzce t pu t pd i sb i cc data out oe ce and lb or ub current read cycle no.2 (either port ce /oe access) [23, 26, 27] ub or lb data out t rc address t aa t oha ce t lzce t abe t hzce t hzce t ace t lzce read cycle no. 3 (either port) [23, 25, 26, 27]
cy7c024av/025av/026av cy7c0241av/0251av/036av 10 preliminary notes: 28. r/w must be high during all address transitions. 29. a write occurs during the overlap (t sce or t pwe ) of a low ce or sem and a low ub or lb . 30. t ha is measured from the earlier of ce or r/w or (sem or r/w ) going high at the end of write cycle. 31. if oe is low during a r/w controlled write cycle, the write pulse width must be the larger of t pwe or (t hzwe + t sd ) to allow the i/o drivers to turn off and data to be placed on the bus for the required t sd . if oe is high during an r/w controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t pwe . 32. to access ram, ce = v il , sem = v ih . 33. to access upper byte, ce = v il , ub = v il , sem = v ih . to access lower byte, ce = v il , lb = v il , sem = v ih . 34. transition is measured 500 mv from steady state with a 5-pf load (including scope and jig). this parameter is sampled and not 100% tested. 35. during this period, the i/o pins are in the output state, and input signals must not be applied. 36. if the ce or sem low transition occurs simultaneously with or after the r/w low transition, the outputs remain in the high-impedance state. switching waveforms (continued) t aw t wc t pwe t hd t sd t ha ce r/w oe data out data in address t hzoe t sa t hzwe t lzwe write cycle no.1: r/w controlled timing [28, 29, 30, 31] [34] [34] [31] [32,33] note 35 note 35 t aw t wc t sce t hd t sd t ha ce r/w data in address t sa write cycle no. 2: ce controlled timing [28, 29, 30, 36] [32,33]
cy7c024av/025av/026av cy7c0241av/0251av/036av 11 preliminary notes: 37. ce = high for the duration of the above timing (both write and read cycle). 38. i/o 0r = i/o 0l = low (request semaphore); ce r = ce l = high. 39. semaphores are reset (available to both ports) at cycle start. 40. if t sps is violated, the semaphore will definitely be obtained by one side or the other, but which side w ill get the semaphore is unpredictable. switching waveforms (continued) t sop t saa valid adress valid adress t hd data in va lid data out valid t oha t aw t ha t ace t sop t sce t sd t sa t pwe t swrd t doe write cycle read cycle oe r/w i/o 0 sem a 0 ? a 2 semaphore read after write timing, either side [37] match t sps a 0l ? a 2l match r/w l sem l a 0r ? a 2r r/w r sem r timing diagram of semaphore contention [38, 39, 40]
cy7c024av/025av/026av cy7c0241av/0251av/036av 12 preliminary note: 41. ce l = ce r = low. switching waveforms (continued) va lid t ddd t wdd match match r/w r data in r data outl t wc address r t pwe va lid t sd t hd address l t ps t bla t bha t bdd busy l timing diagram of read with busy (m/s =high) [41] t pwe r/w busy t wb t wh write timing with busy input (m/s =low)
cy7c024av/025av/026av cy7c0241av/0251av/036av 13 preliminary note: 42. if t ps is violated, the busy signal w ill be asserted on one side or the other, but there is no guarantee to which side busy will be asserted. switching waveforms (continued) address match t ps t blc t bhc address match t ps t blc t bhc ce r valid first: address l,r busy r ce l ce r busy l ce r ce l address l,r busy timing diagram no.1 (ce arbitration) [42] ce l valid first: address match t ps address l busy r address mismatch t rc or t wc t bla t bha address r address match address mismatch t ps address l busy l t rc or t wc t bla t bha address r right address valid first: busy timing diagram no.2 (address arbitration) [42] left address valid first:
cy7c024av/025av/026av cy7c0241av/0251av/036av 14 preliminary notes: 43. t ha depends on which enable pin (ce l or r/w l ) is deasserted first. 44. t ins or t inr depends on which enable pin (ce l or r/w l ) is asserted last. switching waveforms (continued) interrupt timing diagrams write 1fff (or 1/3fff) t wc right side clears int r : t ha read 7fff t rc t inr write 1ffe (or 1/3ffe) t wc right side sets int l : left side sets int r : left side clears int l : read 7ffe t inr t rc address r ce l r/w l int l oe l address r r/w r ce r int l address r ce r r/w r int r oe r address l r/w l ce l int r t ins t ha t ins (or 1/3fff) or 1/3ffe) [43] [44] [44] [44] [43] [44]
cy7c024av/025av/026av cy7c0241av/0251av/036av 15 preliminary architecture the cy7c024av/025av/026av and cy7c0241av/0251av/ 036av consist of an array of 4k, 8k, and 16k words of 16 and 18 bits each of dual-port ram cells, i/o and address lines, and control signals (ce , oe , r/w ). these control pins permit inde- pendent access for reads or writes to any location in memory. to handle simultaneous writes/reads to the same location, a busy pin is provided on each port. two interrupt (int ) pins can be utilized for port-to-port communication. two semaphore (sem ) control pins are used for allocating shared resources. with the m/s pin, the devices can function as a master (busy pins are outputs) or as a slave (busy pins are inputs). the devices also have an automatic power-down feature controlled by ce . each port is provided with its own output enable control (oe ), which allows data to be read from the device. functional description write operation data must be set up for a duration of t sd before the rising edge of r/w in order to guarantee a valid write. a write operation is controlled by either the r/w pin (see write cycle no. 1 wave- form) or the ce pin (see write cycle no. 2 waveform). required inputs for non-contention operations are summarized in table 1 . if a location is being written to by one port and the opposite port attempts to read that location, a port-to-port flowthrough delay must occur before the data is read on the output; other- wise the data read is not deterministic. data will be valid on the port t ddd after the data is presented on the other port. read operation when reading the device, the user must assert both the oe and ce pins. data will be available t ace after ce or t doe after oe is asserted. if the user wishes to access a semaphore flag, then the sem pin must be asserted instead of the ce pin, and oe must also be asserted. interrupts the upper two memory locations may be used for message passing. the highest memory location (fff for the cy7c024av/41av, 1fff for the cy7c025av/51av, 3fff for the cy7c026av/36av) is the mailbox for the right port and the second-highest memory location (ffe for the cy7c024av/ 41av, 1ffe for the cy7c025av/51av, 3ffe for the cy7c026av/36av) is the mailbox for the left port. when one port writes to the other port ? s mailbox, an interrupt is generated to the owner. the interrupt is reset when the owner reads the contents of the mailbox. the message is user defined. each port can read the other port ? s mailbox without resetting the interrupt. the active state of the busy signal (to a port) prevents the port from setting the interrupt to the winning port. also, an active busy to a port prevents that port from reading its own mailbox and, thus, resetting the interrupt to it. if an application does not require message passing, do not con- nect the interrupt pin to the processor ? s interrupt request input pin. the operation of the interrupts and their interaction with busy are summarized in table 2. busy the cy7c024av/025av/026av and cy7c0241av/0251av/ 036av provide on-chip arbitration to resolve simultaneous memory location access (contention). if both ports ? ce s are asserted and an address match occurs within t ps of each oth- er, the busy logic will determine which port has access. if t ps is violated, one port will definitely gain permission to the loca- tion, but it is not predictable which port will get that permission. busy will be asserted t bla after an address match or t blc after ce is taken low. master/slave a m/s pin is provided in order to expand the word width by configuring the device as either a master or a slave. the busy output of the master is connected to the busy input of the slave. this will allow the device to interface to a master device with no external components. writing to slave devices must be delayed until after the busy input has settled (t blc or t bla ), otherwise, the slave chip may begin a write cycle during a con- tention situation. when tied high, the m/s pin allows the de- vice to be used as a master and, therefore, the busy line is an output. busy can then be used to send the arbitration out- come to a slave. semaphore operation the cy7c024av/025av/026av and cy7c0241av/0251av/ 036av provide eight semaphore latches, which are separate from the dual-port memory locations. semaphores are used to reserve resources that are shared between the two ports. the state of the semaphore indicates that a resource is in use. for example, if the left port wants to request a given resource, it sets a latch by writing a zero to a semaphore location. the left port then verifies its success in setting the latch by reading it. after writing to the semaphore, sem or oe must be deassert- ed for t sop before attempting to read the semaphore. the semaphore value w ill be available t swrd + t doe after the rising edge of the semaphore write. if the left port was successful (reads a zero), it assumes control of the shared resource, oth- erwise (reads a one) it assumes the right port has control and continues to poll the semaphore. when the right side has re- linquished control of the semaphore (by writing a one), the left side will succeed in gaining control of the semaphore. if the left side no longer requires the semaphore, a one is written to cancel its request. semaphores are accessed by asserting sem low. the sem pin functions as a chip select for the semaphore latches (ce must remain high during sem low). a 0 ? 2 represents the semaphore address. oe and r/w are used in the same man- ner as a normal memory access. when writing or reading a semaphore, the other address pins have no effect. when writing to the semaphore, only i/o 0 is used. if a zero is written to the left port of an available semaphore, a one will appear at the same semaphore address on the right port. that semaphore can now only be modified by the side showing zero (the left port in this case). if the left port now relinquishes con- trol by writing a one to the semaphore, the semaphore will be set to one for both sides. however, if the right port had request- ed the semaphore (written a zero) while the left port had con- trol, the right port would immediately own the semaphore as soon as the left port released it. ta b l e 3 shows sample sema- phore operations. when reading a semaphore, all sixteen/eighteen data lines output the semaphore value. the read value is latched in an output register to prevent the semaphore from changing state during a write from the other port. if both ports attempt to ac- cess the semaphore within t sps of each other, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore.
cy7c024av/025av/026av cy7c0241av/0251av/036av 16 preliminary table 1. non-contending read/write inputs outputs ce r/w oe ub lb sem i/o 9 ? i/o 17 i/o 0 ? i/o 8 operation h x x x x h high z high z deselected: power-down x x x h h h high z high z deselected: power-down l l x l h h data in high z write to upper byte only l l x h l h high z data in write to lower byte only l l x l l h data in data in write to both bytes l h l l h h data out high z read upper byte only l h l h l h high z data out read lower byte only l h l l l h data out data out read both bytes x x h x x x high z high z outputs disabled h h l x x l data out data out read data in semaphore flag x h l h h l data out data out read data in semaphore flag h x x x l data in data in write d in0 into semaphore flag x x h h l data in data in write d in0 into semaphore flag l x x l x l not allowed l x x x l l not allowed table 2. interrupt operation example (assumes busy l =busy r =high) [45] left port right port function r/w l ce l oe l a 0 l ? 13 l int l r/w r ce r oe r a 0r ? 13r int r set right int r flag l l x fff [48] x x x x x l [47] reset right int r flag x x x x x x l l fff (or 1/3fff) h [46] set left int l flag x x x x l [46] l l x 1ffe (or 1/ 3ffe) x reset left int l flag x l l 1ffe [48] h [47] x x x x x table 3. semaphore operation example function i/o 0 ? i/o 17 left i/o 0 ? i/o 17 right status no action 1 1 semaphore free left port writes 0 to semaphore 0 1 left port has semaphore token right port writes 0 to semaphore 0 1 no change. right side has no write access to semaphore left port writes 1 to semaphore 1 0 right port obtains semaphore token left port writes 0 to semaphore 1 0 no change. left port has no write access to semaphore right port writes 1 to semaphore 0 1 left port obtains semaphore token left port writes 1 to semaphore 1 1 semaphore free right port writes 0 to semaphore 1 0 right port has semaphore token right port writes 1 to semaphore 1 1 semaphore free left port writes 0 to semaphore 0 1 left port has semaphore token left port writes 1 to semaphore 1 1 semaphore free notes: 45. see functional description for specific highest memory locations by device. 46. if busy r =l, then no change. 47. if busy l =l, then no change. 48. see functional description for specific addresses by device.
cy7c024av/025av/026av cy7c0241av/0251av/036av 17 preliminary ordering information document #: 38 ? 00838 4k x16 3.3v asynchronous dual-port sram speed (ns) ordering code package name package type operating range 15 [1] cy7c024av-15ac a100 100-pin thin quad flat pack commercial 20 cy7c024av-20ac a100 100-pin thin quad flat pack commercial 25 cy7c024av-25ac a100 100-pin thin quad flat pack commercial 8k x16 3.3v asynchronous dual-port sram speed (ns) ordering code package name package type operating range 15 [1] cy7c025av-15ac a100 100-pin thin quad flat pack commercial 20 cy7c025av-20ac a100 100-pin thin quad flat pack commercial 25 cy7c025av-25ac a100 100-pin thin quad flat pack commercial 16k x18 3.3v asynchronous dual-port sram speed (ns) ordering code package name package type operating range 15 [1] cy7c026av-15ac a100 100-pin thin quad flat pack commercial 20 cy7c026av-20ac a100 100-pin thin quad flat pack commercial 25 cy7c026av-25ac a100 100-pin thin quad flat pack commercial cy7c026av-25ai a100 100-pin thin quad flat pack industrial 4k x18 3.3v asynchronous dual-port sram speed (ns) ordering code package name package type operating range 15 [1] cy7c0241av-15ac a100 100-pin thin quad flat pack commercial 20 cy7c0241av-20ac a100 100-pin thin quad flat pack commercial 25 cy7c0241av-25ac a100 100-pin thin quad flat pack commercial 8k x18 3.3v asynchronous dual-port sram speed (ns) ordering code package name package type operating range 15 [1] cy7c0251av-15ac a100 100-pin thin quad flat pack commercial 20 cy7c0251av-20ac a100 100-pin thin quad flat pack commercial 25 cy7c0251av-25ac a100 100-pin thin quad flat pack commercial 16k x18 3.3v asynchronous dual-port sram speed (ns) ordering code package name package type operating range 15 [1] cy7c036av-15ac a100 100-pin thin quad flat pack commercial 20 cy7c036av-20ac a100 100-pin thin quad flat pack commercial 25 cy7c036av-25ac a100 100-pin thin quad flat pack commercial cy7c036av-25ai a100 100-pin thin quad flat pack industrial shaded areas contain advance information.
cy7c024av/025av/026av cy7c0241av/0251av/036av preliminary ? cypress semiconductor corporation, 1999. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. package diagram 100-pin thin plastic quad flat pack (tqfp) a100 51-85048-b

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